The present invention is concerned with semiconductor fabrication and particularly with design rules involving contact window placement and etching, as well as other aspects of the fabrication of integrated circuits.
A first problem which the present invention addresses relates to the fabrication of contact windows, which becomes a substantial problem in high-density integrated circuits. Integrated circuits are layered, having a silicon substrate, a first and sometimes a second layer of polysilicon thereover, and at least one layer of metal over that. Each of these layers is "defined" into circuit elements (such as lines). In order to provide electrical insulation between these various elements and layers, interlevel dielectric is used between the elements defined in the first (lowest or first deposited) polysilicon layer (poly I) and elements defined in the second polysilicon layer (poly II), between poly II and the elements defined in the first metal layer, and between elements defined in subsequent metal layers. Contact windows permit contacts between two layers or between a part of the substrate and a layer or element located above it.
One use for a contact window is to provide electrical contact with a source/drain region which has been formed in a substrate. Near the contact window there will generally be found another element such as a gate electrode, a field shield edge, or a field oxide edge. with the increasing density of integrated circuits, the geometries become smaller, and obviously the space separating the contact windows from nearby elements becomes less. To understand this problem, reference will be made to FIGS. 1A-1D.
FIG. 1A is a representational plan view of a contact window 1 which is placed on a source/drain region 2 (inside broken lines) which has been established within a substrate 3. Window 1 is located a distance d represented by an arrow 4 from an edge 5 which separates source/drain region 2 from isolation 6. Isolation 6 covers substrate 3 outside of the source/drain region 2. A polysilicon line 7 forms a gate electrode where it passes over an active area defined by edge 5. As illustrated in FIG. 1A, the contact window is an adequate distance d away from edge 5.
However, in FIG. 1B contact window 1 has not been aligned properly with respect to source/drain region 2. While it does predominantly lie upon region 2 and therefore will permit subsequently added metal to contact source/drain 2, window 1 has no separation from edge 5 and indeed is partially lying on top of isolation 6. Because the contact window is an etched opening which will be filled by a conductive metal, if part of isolation 6 (either a field shield gate electrode or the substrate underlying a field oxide) is exposed by contact window 1 as in FIG. 1B, then when the metal is added, isolation element 6 (or the material beneath it) will be shorted to the source/drain region 2 and to the metal interconnect. Obviously, this is to be avoided.
The problem is further illustrated in FIGS. 1C and 1D. A cross-sectional view along line A--A of FIG. 1B is shown in FIG. 1C where element 6 is shown illustratively as a field shield electrode 6a (defined in poly I) next to a source/drain region 2 in the substrate 3. (For a discussion of field shield electrodes, see U.S. Pat. No. 4,570,331 filed Jan. 26, 1984, Pat. No. 4,570,331, entitled "Thick Oxide Field-Shield CMOS Process" which is incorporated herein by reference). A gate electrode 7 (defined in poly II) is shown above and adjacent to source/drain region 2. Over substrate 3 and on top of field shield electrode 6a and gate electrode 7 is shown a representative thickness of oxide 8. Contact window 1 has been formed beneath an arrow 9 which represents the positioning of the contact window as set up by the fabrication equipment. It can be seen in FIG. 1C that part of field shield electrode 6a has been exposed by etching oxide 8 to create contact window 1. When metal is added, it will short electrode 6a to source/drain region 2. It will be apparent that, in the same manner, where contact window 1 is misaligned such that it lays over the edge of electrode 7, the edge of electrode 7 would be exposed by etching oxide 8 to open contact window 1, and again a short would occur.
A variation is shown in FIG. 1D, which is also a cross-sectional view along line A--A of FIG. 1B. However, in this case element 6 refers illustratively to a field oxide 6b next to source/drain region 2 in substrate 3. Gate electrode 7 next to the source/drain region 2 and oxide 8 are included. Contact window 1 has been formed beneath arrow 9 which represents the positioning of the contact window as set up by the fabrication equipment.
It can be seen in FIG. 1D that part of the field oxide 6b under arrow 9 has been removed by etching through oxide 8 to open contact window 1. (Dotted line 6' shows the original thickness of field oxide 6b before the contact window was etched.) Some field oxide 6b was removed because it cannot be distinguished during etching from oxide 8.
Integrated circuits are formed on large substrates (4" to 8" in diameter) which contain typically hundreds of circuits and typically million of contact windows. Since a material cannot be deposited or grown uniformly in thickness over such a large area (at worst .+-.10%), an overetch of 20% is common to insure that all contact windows on the entire substrate will be etched open.
In FIG. 1D the edge of field oxide 6b is tapered, as is common when the field oxide/active area pattern is formed by local oxidation of silicon. The misalignment of contact window 1 illustrated by arrow 9 has exposed the tapered thin edge 6bb of field oxide 6b to the contact window etch. Since the etch cannot distinguish between field oxide 6b and oxide 8 and an overetch is required or ordinarily employed, a region 3' of substrate 3 which does not include source/drain 2 has been exposed. When metal is added, it will short substrate 3 to source/drain region 2.
In current high density dynamic random access memories, a contact window will be on the order of 1.0 to 1.5 microns in length and width. Often it will be located on an active area next to a polysilicon word line and isolation edge, such as element 7 and line 5 in FIGS. 1A, 1B, 1C, and 1D. Perpendicular to the word line will be a bit line formed in an upper layer of metal. At this intersection of the bit line and word line will be a memory cell. The contact window will allow the metal from the bit line to contact the source/drain region. The contact window may be separated by only about 1 micron from the polysilicon word line and the isolation edge.
However, the size of the contact window 1 itself has tolerances in its fabrication so that its actual dimensions may be up to 0.5 microns larger than the specified dimension for the contact window. If the contact window is larger than specified, it will be closer to the polysilicon word line and the isolation edge.
Accordingly, it is necessary to locate the contact window so as not to cause a short. One commonly desires to align the contact window to some known edge, typically one edge of a gate electrode or an isolation edge (e.g., an edge of field shield 6a or field oxide 6b). However, there is a nonzero tolerance in aligning one level to the next level in forming an integrated circuit. This tolerance t (typically 0.5 microns for minimum feature sizes in the 1-2 micron range) is inherent in the wafer stepper equipment used for fabrication. If there were a misalignment of the contact window with respect to an isolation edge or other element, this could result in an undesired short unless there were a wide margin of error.
Consider with respect to FIG. 1A that contact window 1 is to be aligned with respect to a sharp edge in any given layer, for example, edge 5. To prevent contact window 1 from unintentionally contacting isolation 6 to the right of line 5 despite the position tolerance t, then the design rule for positioning the window would require it to be located nominally at a distance of at least t from edge 5.
The problem of alignment tolerance becomes more severe with the use of multiple layers. If a contact window is aligned to an element in Poly I, because there is a similar tolerance t also between poly I and poly II, there will be an even larger uncertainty (slightly less than 2t) of the location of the contact window with respect to the elements formed in Poly II. Similarly, if the contact window is aligned to an element defined in the substrate such as a field oxide edge, there will be an uncertainty of approximately 2t in the placement of the contact window with respect to the edge of poly I and poly II (provided they are both aligned to the field oxide edge). In practice, the contact windows are aligned to the most critical layer, with a distance separating the contact from elements defined in that layer of greater than t. The distance separating the contacts from elements formed in other layers is then much larger than t.
Considering all of these tolerances, then, in order to ensure that the metal does not short to any polysilicon feature or the substrate through the contact window, wide margins would be necessary between contact windows and nearby elements. This would increase the size of the integrated circuit significantly, resulting in fewer die per wafer and lower yield.
Such design rules, imposed by the tolerance obtained on optical alignment equipment and in the fabrication process, lead to wasted or unnecessarily large chip areas. These design rules prevent designs from being scaled as aggressively as posssible. A design rule requiring an active area opening to be large could be relaxed if it were possible to provide self-alignment of the contact window with respect to a nearby element to which contact is to be avoided. In other words, it would be advantageous to permit variation in the position of a contact window with respect to the edge of active area or source/drain, even to the extent of allowing it to overlap a polysilicon or other element, provided that there would be not short circuit occasioned by the overlap. Some technique to prevent such shorting would be highly desirable, but no solution suitable for aligning contact windows to gate electrode edges or isolation edges for a VLSI process has come forth.
One possible solution referred to in Batra U.S. Pat. No. 4,466,172 has been devised for self-aligning contact windows to polysilicon gate electrodes. This involves using a nitride/oxide gate dielectric so that oxidation of the polysilicon gate electrode can be achieved with oxide grown on the tops and sides of the polysilicon elements and not on the source and drain regions of the substrate. An etch stop layer of nitride is then added over the structure and interlevel dielectric is then deposited. Contact windows are patterned and etched down to the nitride etch stop layer. Then the etch stop layer is removed where exposed by the contact window. Then the oxide over the source/drain is removed and metal is deposited. The differential between the thickness of oxide on the source/drains versus that on the top and sides of the polysilicon gate electrode results in contact being made to the source/ drain region but not to the polysilicon gate electrode.
However, the use of this approach has been forestalled in fabricating circuits of VLSI dimensions for several reasons. First, the use of nitride/oxide under the gate electrode is not common and is usually not desirable for standard n-channel, p-channel, and CMOS processes. Such a nitride/oxide gate dielectric is used in the prior art to prevent oxidation of the source/drain region while a thick oxide, of "critical importance" (Batra, col. 3, line 6) is grown on the top and sides of the polysilicon electrode. This thick oxide protects the gate electrode from making contact with the metal.
However, this oxide is subjected to hydrofluoric acid (HF) during the removal of the gate oxide. It is well known that oxides grown on polysilicon when subjected to HF solution have a much increased pinhole density over those same oxides as grown. These pinholes will result in shorts between the metal and polysilicon when the metal is added. In addition, VLSI circuits are frequently fabricated with gate electrode materials which are not conveniently oxidized, such as polycide structures and silicides. This raises a problem for the Batra process. Also, transistor structures optimized for 1 micron and submicron channel lengths, such as lightly doped drain structures, require sidewall spacers which are not generally grown but are deposited and are of a specific thickness (0.1-0.5 microns) determined from the desired device characteristics. These sidewall spacers are probably inadequate to prevent metal to gate shorts. The use of the Batra process is not compatible with the formation of these devices. Finally, for transistors in the VLSI regime (under 2 micron poly width) the sidewall oxide required by Batra consumes too much space. Hence, no manufacturable, commercially acceptable process is apparent for permitting self-aligned contact windows in such structures. Aggressive design rule scaling with respect to contact window spacing is not possible when thick interlevel dielectric is used.
One object of this invention therefore is to provide a self-aligned contact process which is independent of gate dielectric type.
Another object of the present invention is to provide a process for self-aligned contacts in a VLSI circuit which is independent of sidewall processes (on the gate electrode) used to optimize device performance. For example, the process should tolerate the absence of unnecessary or undesirable oxide on the sidewalls (unlike Batra). Presently, it is undesirable to oxidize some polycide gate electrodes such as titanium silicide. The process should also tolerate, on the other hand, the addition of any amount of oxide to the sidewall for any purpose such as isolation from a later established interconnect or other element, or the addition of any material to the sidewall for the purpose of providing a spacer to fabricate optimized VLSI transistor structures such as double diffused drain or lightly doped drain devices.
Therefore, another object of the present invention is to provide a process for locating and etching contact windows in transistors without imposing a design rule requiring wasted silicon area, and which can be applied to all gate and field oxide or field shield edge simultaneously.
Another object of the invention is to provide a technique for self-aligning contacts in a semiconductor structure despite the use of interlevel dielectric, which ordinarily is relatively thick.
A further object is to provide a method which permits reliable etching of the contact window despite tolerances in its placement, without jeopardizing the integrity of the memory cell, transistor or other device.